This invention relates generally to CMOS semiconductor transistors and circuits, and more particularly the invention relates to CMOS transistors having dual work function metal gates and methods of manufacturing the same.
In producing high performance bulk CMOS integrated circuits, both n-MOS and pMOS transistors must have low threshold voltages (VT). This in turn requires that the gate electrodes for the n-MOS and p-MOS transistors have different work functions. The desired work function for n-MOS transistors is around 4.1 V and the desired work function for pMOS transistors is around 5.2 V.
Polycrystalline silicon has remained the gate electrode material of choice for many years. The work function of the polycrystalline silicon can be varied from approximately 4.1 to 5.2 V by implanting either donor (n) or acceptor (p) atoms respectively. As device scaling continues beyond the 100 nm technology node, polycrystalline silicon might no longer remain the best choice for this application. The resistance of the polycrystalline silicon gate electrode is limited by the electrically active dopant concentration that can be obtained in the gate. Metal gate electrodes overcome these limitations, due to high free electron concentration in the metallic materials. Polycrystalline silicon is also unstable on the many advanced (high permittivity) gate dielectrics.
Further, as the channeling of CMOS transistors continues to be scaled beyond 100 nm, the capacitance equivalent thickness (CET) of the gate dielectric has to be reduced to less than 15 Å. One way to decrease the CET while maintaining acceptable gate leakage is to use high-k dielectrics instead of silicon oxide. Another way is to replace the polysilicon gate with a metal gate, as noted above, thus eliminating depletion at the gate/dielectric interface and reducing the CET by a couple of angstroms. In addition, metal gate materials may ultimately be necessary for high-k gate dielectrics because polycrystalline silicon has been found to be thermodynamically unstable on some high-k materials such as Ta2O5 and ZrO2. In order to achieve surface-channel p- and n-MOSFETs with low and symmetrical threshold voltages, two different metals with different work functions must be used in a metal gate CMOS technology. A straightforward process for dual-metal gate technology includes blanket deposition of a first gate metal followed by selectively removing the first metal from either the n-MOS or p-MOS regions. Thereafter, a second gate metal is deposited over the entire wafer. Afterwards, the n-MOS and p-MOS gate electrodes are patterned. Unfortunately, this approach exposes the gate dielectric to a metal-etching process in the regions from which the first gate metal is selectively removed, and consequently causes undesirable thinning of the gate dielectric and potential reliability problems.
The present invention is directed to an improved method of fabricating dual metal gates for CMOS transistors and the resulting structures.